ATA8743-PXQW【PDF 50/238 页】MCU W/TRANSMITTER ASK/FSK 24QFN

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Sheet目录52

46页 47页 48页 49页 [50页]51页 52页 53页 54页

9152BINDCO02/10

ATA8743

15. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides various sleep modes allowing the user to tailor the power consump-

tion to the applications requirements.

15.1 Sleep Modes

Figure 14-1 on page 41 presents the different clock systems in the ATtiny24/44/84, and their dis-

tribution. The figure is helpful in selecting an appropriate sleep mode. Table 15-1 shows the

different sleep modes and their wake up sources

Note:

1. For INT0, only level interrupt.

2. Only recommended with external crystal or resonator selected as clock source

To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a

SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which

sleep mode (Idle, ADC Noise Reduction, Standby or Power-down) will be activated by the

SLEEP instruction. See Table 15-2 on page 53 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

15.2 Idle Mode

When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the

interrupt system to continue operating. This sleep mode basically halts clk

CPU

and clk

FLASH

, while

allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,

Table 15-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes

Active Clock Domains

Oscillators

Wake-up Sources

Sleep Mode

Idle

ADC Noise

Reduction

(1)

Power-down

(1)

Stand-by

(2)

(1)

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